ARTICLE | doi:10.20944/preprints202107.0403.v1
Online: 19 July 2021 (10:51:37 CEST)
This paper describes a new optimization methodology of testing vector sets reduction for testing of soft-processor cores and their individual blocks. The deterministic test vectors both for whole core and its individual blocks are investigated that significantly reduce the testing time and amount of test data that needs to be stored on the tester memory. The processor executes an assembler program which together with determined testing vectors ex-ercise its functionality. The new BIST methodology applicable at industrial testing of processor cores, diagnostics and dynamic reconfiguration of FPGA is proposed. This novel methodology combined with dynamic reconfiguration of FPGAs can be profitable applied for missions-critical i.e. FPGAs operate in space, or other difficult condition where are explore on radiation. Experimental results demonstrate that the proposed approach reduces many times testing time.
ARTICLE | doi:10.20944/preprints201609.0020.v1
Online: 6 September 2016 (11:51:45 CEST)
A portable laser photoacoustic sensor based on a Field-Programmable Gate Array (FPGA) is reported for methane detection. A tunable DFB diode laser in the 1654 nm wavelength range is used as an excitation source. The photoacoustic signal processing was implemented by a FPGA device. A small resonant photoacoustic cell is designed. The minimum detection limit (1σ) of 10 ppm for methane (CH4) is demonstrated.
ARTICLE | doi:10.20944/preprints202003.0397.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: New-CFAR; WS-CFAR; FPGA; Radar detection
Online: 26 March 2020 (15:38:32 CET)
In the radar system, detection represents a basic and important stage in the receiver side. The detection process is based on the thresholding criteria; two philosophies of this criteria, constant and adaptive threshold. The constant threshold is simple in design, but it has a mis-detection and does not control the false alarm rate. As for the adaptive threshold, it is powerful in target detection, and better control of the false alarm rate, where it is called Constant False Alarm Rate (CFAR). Lots of research in the CFAR design, but the gap in the previous works is that there is no CFAR algorithm can be working with all or most environmental fields and all or most target situations.In this paper, The CFAR, which can work with the most environment and most of the target situations, has been presented. The producing the design and implementation of the new practical CFAR processor is presented. Where, the new CFAR is a combination of the properties of three different CFAR algorithm (CA, OSGO, and OSSO), and from two different families; averaging and statistical. Where it has overperformed of it's is 97.25% for simulation and 96.25% for the implementable version for different target situations. The simulation analysis is made by using Matlab 2015, while the implementation is done by using Xilinx Spartan 700 3a.
ARTICLE | doi:10.20944/preprints201804.0101.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: EMI; Luo-converter; chaotic PWM technique; FPGA; RCFMFD
Online: 9 April 2018 (09:00:19 CEST)
Chaotic switching is a newly evolve randomization method which can suppress conducted electromagnetic interference generated within the DC-DC converter. It can suppress the spectral peaks present in the frequency band effectively by spread spectrum technique and can spread it over the wide range of frequency band implying EMI suppression. In this paper, a chaotic PWM technique based on RCFMFD scheme is generated through Field programmable gate array (FPGA) for suppressing the conducted electromagnetic interference (EMI) generated within the Luo converter. A hardware prototype of Luo converter was developed in order to analyze EMI reduction through FFT analysis by comparing both traditional periodic PWM switching and chaotic PWM switching. The results obtained from the hardware setup shows significant reduction of EMI with Chaotic switching as compared to traditional PWM switching for both boost and buck operation of Luo converter.
ARTICLE | doi:10.20944/preprints202110.0098.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: FPGA; Wishbone; Control interface; VHDL; System management; System diagnostics
Online: 6 October 2021 (09:48:08 CEST)
FPGA-based data acquisition and processing systems play an important role in modern high-speed, multichannel measurement systems, especially in High-Energy and Plasma Physics. Such FPGA-based systems require an extended control and diagnostics part corresponding to the complexity of the controlled system. Managing the complex structure of registers while keeping the tight coupling between hardware and software is a tedious and potentially error-prone process. Various existing solutions aimed at helping that task do not perfectly match all specific requirements of that application area. The paper presents a new solution based on the XML system description, facilitating the automated generation of the control system’s HDL code and software components and enabling easy integration with the control software. The emphasis is put on reusability, ease of maintenance in case of system modification, easy detection of mistakes, and the possibility of use in modern FPGAs. The presented system has been successfully used in data acquisition and preprocessing projects in High-Energy Physics experiments. It enables easy creation and modification of the control system definition and convenient access to the control and diagnostic blocks. The presented system is an open-source solution and may be adopted by the user for particular needs.
Subject: Physical Sciences, Optics Keywords: magnetic fusion devices; ir interferometry; fpga; phase detection; dsp
Online: 20 September 2019 (10:32:16 CEST)
Interferometry is used in magnetic fusion devices to measure the line-1 averaged electron density. It is based on detecting changes in the refractive index of electromagnetic waves traveling through a plasma. The adequate frequency of these electromagnetic waves depends on several limitations. First the maximum expected peak electronic density must be lower than the cutoff density for that frequency. This means that the waves can still propagate through the plasma when the maximum density is reached. In this sense, IR interferometers operating in the infrared región are themost suitable. With such low wavelengths, mechanical vibrations become an important issue and a complementary interferometer to cancel these vibrations must be used. These arrangements are called two color interferometers. In this paper some measurements that were obtained from the TJ-II double color IR FPGA-based processing system that were never published before are shown and analyzed. The line-averaged electron density is computed in real time (100 μs).
ARTICLE | doi:10.20944/preprints201806.0393.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: reconfigurable architecture; CORDIC; Field Programmable Gate Array(FPGA); SAR imaging
Online: 25 June 2018 (14:42:01 CEST)
This paper presents a unified reconfigurable coordinate rotation digital computer (CORDIC) processor for floating-point arithmetic. It can be configured to operate in multi-mode to achieve a variety of operations and replaces multiple single-mode CORDIC processors. A reconfigurable pipeline-parallel mixed architecture is proposed to adapt different operations, which maximizes the sharing of common hardware circuit and achieves the area-delay-efficiency. Compared with previous unified floating-point CORDIC processors, the consumption of hardware resources is greatly reduced. As a proof of concept, we apply it to 1638416384 points target Synthetic Aperture Radar (SAR) imaging system, which is implemented on Xilinx XC7VX690T FPGA platform. The maximum relative error of each phase function between hardware and software computation and the corresponding SAR imaging result can meet the accuracy index requirements.
ARTICLE | doi:10.20944/preprints201907.0011.v1
Subject: Keywords: LTE, LTE-A, 4G, PRACH, NCO, time-domain frequency shift, FPGA
Online: 1 July 2019 (11:52:58 CEST)
The Physical Random Access Channel (PRACH) plays an important role in LTE and LTE-A systems. It is through the PRACH channel that the user equipment (UE), based on eNodeB's timing estimates, aligns its uplink transmissions to the eNodeB's uplink and gain access to the network. One of the initial operations executed by the PRACH receiver at eNodeB side is the translation of the PRACH signal back to base band, $i.e.$, center the PRACH signal around DC. This operation is a necessary step for preamble detection and can be carried out through a time-domain frequency shift operation. Therefore, in this paper we present the hardware architecture and implementation details of a configurable and optimized FPGA-based time-domain frequency shifter. It is a hardware-efficient and accurate architecture for converting the relevant received PRACH signal into base band before further signal processing. The architecture is manly based on a customized Numerically Controlled Oscillator (NCO), which is used for generating complex exponentials employing only adders, a Look-Up Table (LUT) and plain logic resources. The main advantage of the proposed hardware architecture is that it completely eliminates the need for storing a large number of long complex exponential sequences by employing a single LUT and exploiting quarter wave symmetry of the basis waveform. Our simulation results show that the proposed customized NCO architecture provides high Spurious Free Dynamic Range (SFDR) signals using a minimal amount of FPGA resources. Moreover, the proposed architecture exhibits spur-suppression ranging from 62.13 to 153.58 dB without using Taylor Series correction.
ARTICLE | doi:10.20944/preprints201804.0129.v1
Subject: Engineering, Control & Systems Engineering Keywords: Topological-entropy; Chaos; Fractional-order; Computer-assisted proof; Topological Horseshoe Analysis; FPGA
Online: 10 April 2018 (15:41:39 CEST)
This paper first discusses a fractional-order Liu system of order as low as 2.7 and shows its chaotic characteristics by carrying out numerical simulations such as Lyapunov exponents, bifurcation diagrams and phase portraits. Then, by using the topological horseshoe theory and computer-assisted proof, the existence of chaos in the system is verified theoretically. Finally, the fractional-order system is implemented on a Field Programmable Gate Array (FPGA) and the results obtained show that the fractional-order Liu system is indeed chaotic.
CONCEPT PAPER | doi:10.20944/preprints202204.0129.v1
Subject: Mathematics & Computer Science, Other Keywords: Digital Design; Digital Architecture; Image Processing; Machine learning; FPGA; Dedicated Design; Image Processor
Online: 14 April 2022 (05:09:47 CEST)
Many dedicated designs for real-time operations provide functionality on fixed-sized operators, but where speed, scalability, and flexibility are required, extensive research is demanded. Dedicated designs can provide real-time processing for many applications. This paper presents an FPGA-based design of a general image processor. The proposed design is based on a fixed-point representation of binary numbers. The proposed design provides a mechanism to manage matrices on-chip along with matrix arithmetic. The matrices are represented with simple identifiers and microinstruction that assist in the computation of many operations which are useful for solving complex problems. The design was successfully implemented and tested using VHDL language. The proposed design is an efficient architecture as a standalone processor with all embedding computational resources necessary for an embedded image processing application.
ARTICLE | doi:10.20944/preprints202101.0202.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: Stochastic Logic; Chaotic Systems; Approximate Computing; Shimizu-Morioka System; Chaotic Circuits; FPGA Implementation
Online: 11 January 2021 (14:56:15 CET)
An exploding demand for processing capabilities related to the emergence of the IoT, AI and big data, has led to the quest for increasingly efficient ways to expeditiously process the rapidly increasing amount of data. These ways include different approaches like improved devices capable of going further in the more Moore path, but also new devices and architectures capable of going beyond Moore and getting more than Moore. Among the solutions being proposed, Stochastic Computing has positioned itself as a very reasonable alternative for low-power, low-area, low-speed, and adjustable precision calculations; four key-points beneficial to edge computing. On the other hand, chaotic circuits and systems appear to be an attractive solution for (low-power, green) secure data transmission in the frame of edge computing and IoT in general. Classical implementations of this class of circuits require intensive and precise calculations. This paper discusses the use of the SC framework for the implementation of nonlinear systems, showing that it can provide results comparable to those of classical integration, with much simpler hardware, paving the way for relevant applications.
ARTICLE | doi:10.20944/preprints202008.0603.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: secure boot; cyber-physical system security; embedded systems; FPGA; hardware primitives; IoT security
Online: 27 August 2020 (08:49:02 CEST)
Reconfigurable computing is becoming ubiquitous in the form of consumer-based Internet of Things (IoT) devices. Reconfigurable computing architectures have found their place in safety-critical infrastructures such as the automotive industry. As the target architecture evolves, it also needs to be updated remotely on the target platform. This process is susceptible to remote hijacking, where the attacker can maliciously update the reconfigurable hardware target with tainted hardware configuration. This paper proposes an architecture of establishing Root of Trust at the hardware level using cryptographic co-processors and Trusted Platform Modules (TPMs) and enable over the air updates. The proposed framework implements secure boot protocol on Xilinx based FPGAs. The project demonstrates the configuration of the bitstream, boot process integration with TPM and secure over-the-air updates for the hardware reconfiguration.
ARTICLE | doi:10.20944/preprints201807.0444.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: staircase waveform; harmonics control; field programming gate array (FPGA); estimation; iterative technique; VHDL
Online: 24 July 2018 (06:07:17 CEST)
Few switching transitions in high power and medium voltage application of Power converters are desirable. The selective harmonics elimination (SHE) pulse width modulation offers a better quality waveform with lower switching transitions and hence lower switching losses. The SHE is a pre-programmed modulation technique where certain amounts of lower order harmonics are removed and fundamental voltage is controlled. After Fourier analysis of output waveform, a set of nonlinear transcendental equations is obtained which exhibits, multiple, unique or no solution in different range of modulation index (MI). In this paper, an iterative method based on the Jacobian estimate is proposed to solve a highly non-linear set of SHE equations. The proposed technique is easy in implementation and can solve a large number of such equations as computation of the Jacobian matrix in the subsequent iteration is estimated from the previous values. Moreover, the proposed method also removes the singularity problem, especially for large SHE equations. High accuracy in the initial guess is also not essential for this method and can converge to the solution with any random initial guess. The computational and simulation results are given to validate the concept. The hardware result is provided to confirm the computational and simulation results.
ARTICLE | doi:10.20944/preprints202201.0399.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: Shared Autonomous Vehicle (SAV); Field-Programmable Gate Array (FPGA); Microphone Array; Sound Source Localization
Online: 26 January 2022 (13:07:39 CET)
With the current technological transformation in the automotive industry, autonomous vehicles are getting closer to the Society of Automative Engineers (SAE) automation level 5. This level corresponds to the full vehicle automation, where the driving system autonomously monitors and navigates the environment. With SAE-level 5, the concept of a Shared Autonomous Vehicle (SAV) will soon become a reality and mainstream. The main purpose of an SAV is to allow unrelated passengers to share an autonomous vehicle without a driver/moderator inside the shared space. However, to ensure their safety and well-being until they reach their final destination, it is required an active monitoring of all passengers. In this context, this article presents a microphone-based sensor system that is able to localize sound events inside an SAV. The solution is composed of a Micro-Electro-Mechanical System (MEMS) microphone array with a circular geometry connected to an embedded processing platform that resorts to Field-Programmable Gate Array (FPGA) technology to successfully process in hardware the sound localization algorithms.
ARTICLE | doi:10.20944/preprints202101.0250.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: elliptic curves cryptography (ECC); high speed implementation; unified; Montgomery multiplication; field-programmable gate array (FPGA)
Online: 13 January 2021 (13:03:15 CET)
In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes DSP primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020, yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.
ARTICLE | doi:10.20944/preprints201809.0550.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: synthetic aperture radar (SAR); real-time processing; single FPGA node imaging processing; multi-node parallel accelerating technique
Online: 27 September 2018 (15:14:49 CEST)
With the development of satellite load technology and very-large-scale integrated (VLSI) circuit technology, on-board real-time synthetic aperture radar (SAR) imaging systems have facilitated rapid response to disasters. Limited by severe size, weight, and power consumption constraints, a key challenge of on-board SAR imaging system design is to achieve high real-time processing performance. In addition, with the rise of multi-mode SAR applications, the reconfiguration of the on-board processing system is beginning to receive widespread attention. This paper presents a multi-mode SAR imaging chip with SoC architecture based on the reconfigurable double-operation engines and multilayer switching network. We decompose the commonly used extend chirp scaling (CS) SAR imaging algorithm into 8 types of double-operation engines according to the computing orders, and design a three-level switching network to connect these engines for data transition. The CPU is responsible for engine scheduling based on data flow driven with instructions to implement each part of the CS algorithm. Thus, multi-mode floating-point SAR imaging processing can be integrated into a single Application-Specific Integrated Circuit (ASIC) chip instead of relying on distributed technologies. As a proof of concept, a prototype measurement system with chip-included board is implemented, and the performance of the proposed design is demonstrated on Chinese Gaofen-3 stripmap continuous imaging. A chip requires 9.2 s, 50.6 s and 7.4 s for a stripmap with 16,384×16,384 granularity, multi-channel stripmap with 65.536×8192 granularity and multi-channel scan mode with 32,768×4096 granularity and 6.9 W for the system hardware to process the SAR raw data.
ARTICLE | doi:10.20944/preprints201702.0050.v1
Subject: Engineering, Electrical & Electronic Engineering Keywords: Digital Lock-in Amplifier (DLIA); Field Programmable Gate Array (FPGA); Near Infrared Spectroscopy (NIRS); Hardware Description Language (HDL); Light Emitting Diode (LED); Silicon Photomultiplier (SiPM); Microprocessors
Online: 14 February 2017 (09:11:38 CET)
Functional Near Infrared Spectroscopy (fNIRS) systems for e-health applications usually suffer of poor signal detection mainly due to a low end-to-end signal to noise ratio of the electronics chain. Lock-In Amplifiers (LIA) historically represent a powerful technique helping to improve performances in such circumstances. In this work it has been designed and implemented a digital LIA system, based on a Zynq® Field Programmable Gate Array (FPGA), trying to explore if this technique might improve fNIRS system performances. More broadly, FPGA based solution flexibility has been investigated, with particular emphasis applied to digital filter parameters, needed in the digital LIA, and it has been evaluated its impact on the final signal detection and noise rejection capability. The realized architecture was a mixed solution between VHDL hardware modules and software ones, running within a softcore microprocessor. Experimental results have shown the goodness of the proposed solutions and comparative details among different implementation will be detailed. Finally a key aspect taken into account throughout the design was its modularity, allowing an ease increase of the input channels while avoiding the growth of the design cost of the electronics system.