Optimal IP Current Controller Design Based on Small Signal Stability for THD Reduction of High-Power Density PFC Boost Converter

This paper presents an optimal design for the inner current control loop of the continuous current conduction mode (CCM) power factor correction (PFC) stage, which it can be used as the front stage of the two stages alternating current-direct current (AC-DC) telecom power supply. Conventional single-phase CCM-PFC boost converter usually implemented with using of the proportional-integral (PI) controllers in both of the voltage and current control loops, to regulate the output DC voltage to the specified value, moreover to maintains the input current follows the input voltage which offers converter with high power factor (P.F) and low current total harmonic distortion (THD). However, due to the slow dynamic response of the PI controller at the zero-crossing point of the input supply current, input current can’t fully follow the input voltage which leads to high THD. Digitally controlled PFC converter with an optimal design of the inner current control loop using doubly control loops IP controller to reduce the THD and to offer input current with unity P.F was performed in this paper. Furthermore, for the economic design of the digitally control PFC converter, two isolated AC and DC voltage sensors are proposed and designed for the interfacing with the microcontroller unit (MCU). PSIM software was used to test the converter performance with using the proposed designed current controllers and isolated voltage sensors. High power density digitally controlled telecom PFC stage with P.F of about 99.93%, full load efficiency of about 98.70% and THD less 5.50% is achieved in this work.

based on the power applications, there are more types of PFC converters which widely used, such as the Conventional PFC boost converter [5][6][7], the bridgeless PFC boost converter [8,9], and the interleaved PFC boost converter [10,11]. For telecom applications, conventional PFC boost converter is the mostly used circuit because its good performance with economic, simplest and less requirements of the power and control circuits design [1,12], the target of this paper is to improve the performance of the telecom power supply conventional PFC stage by optimized the control technique of the boost converter controllers in order to offer converter with unity power factor by reducing the THD of the input supply current.
PFC boost converter controlling circuit can be implemented using the digital or analog techniques, controlling circuit using analog integrated circuits (IC) offers economic design of the converter, otherwise it is having some disadvantages as compared with the digital micro-controller unit (MCU) such as slow response, low operating temperature and fixed control parameters. Digital MCU offers high speed response, flexible adjustment and programming of the control techniques [13], despite all of that, the price of the measurement sensors required for the interface between the converter power circuit and DSP MCU are very expensive as compared with sensors for interfacing with the analog control IC.
Conventional PFC boost converter consisting of power and control circuits, where the power circuit contains the bridge rectifier, energy storage inductor, single switch or multiple switches connected in parallel (to increase the converter current rating), fast switching diode as well as the output bulk capacitor. The PFC boost converter control circuit usually implements with two control loops, the inner current control loop to control the inductor current which making the input current follows the input voltage and maintain the circuit power factor (P.F) at higher values, and the outer voltage loop which maintain the output voltage value as the specified load value, usually these control loops implemented using PI controllers.
For the output voltage control loop, PI controller is enough to regulate the output voltage to the specified value [14], but for the inductor current control loop, the slow response of the PI current controller at the current zero-crossing point causes distortion of the inductor current which leads to increasing the THD of the supply current [15]. Increasing of the THD in the converter circuits, causes higher power losses in all circuit components, further, it can lead to high current stresses and failures of the system insulation and protection [16]. Power quality and performance requirements required to maintain the THD value at the standard values such as IEEE 519-20142 [17], and IEC 61000-3-2 [18], which suggests that in order to improve the circuit P.F, reducing the current stresses and reducing the power losses in the system different parts, THD should be kept at the lowest value with the given standard requirements [17,18].
Reducing of the current THD in the digitally controlled PFC boost converters can be done by using different techniques such as, the passive harmonic filters connecting in parallel with the input side, this technique can be used to reduce the THD in case of the low switching frequency PFC converters, however in case of the high frequency PFC converters where the EMI filters connecting in the input side of the converters, reliability of the passive filters to decrease the THD is very low due to the difficulty of the tuning of the filter's resonance frequency with the presence of the EMI filters [19]. Digital current filters such as finite response impulse (FIR), and infinite impulse response (IIR) filters can be optimally designed and used to moderate the feedback digital current signals for the inner current control loops to reduce the current error and hence reducing the current distortion, using of the adaptive FIR filter to reduce the THD of the CCM-bridgeless PFC converter was proposed in [20].
Another widely used technique to reduce the THD in PFC converters is the variable on-time (VOT) switching control technique by optimized the duty cycle of the PFC converter to decrease zero crossing distortion (ZCD) period [20][21][22][23], VOT switching control technique is reliable to reduce the THD in PFC converter but with complex mathematical analysis of the converter operation around the zero-crossing point in order to optimize the exact dead time around the zero-crossing point for exact on-time switching prediction [24]. This paper presents the small signal stability modeling of the conventional PFC boost converter proposed, and based on the signal stability model, an optimal integral-proportional (IP) current controller consists of double loop control strategy, where the integral gain feed forward to return the inductor current back to the reference set point, and the proportional gain implemented in the feedback path to increase the controller response. IP controller usually used in the control circuits of the DC-DC converters and the DC motor drive systems [25][26][27], as compared with the PI controller, the IP controller have less overshoot and fast dynamic response [28]. So, IP current controller with fast dynamic response has been designed to let the inductor current track the reference current, removing the total distortion occurred around the zero-crossing point and increase the power factor.
The Two different current techniques based on the conventional PI controller and the proposed IP controller have been presented in this paper and the comparative analysis based on the system stability and the controller reliability to reduce the zero-crossing current distortion was performed.
Furthermore, For the economic design of the digitally controlled PFC converter, the isolated voltage sensors with low price components for interfacing with the MCU analog digital converter (ADC) has been proposed, and completely designed.
The following sections in this paper are organized as follow, section 2 explain briefly the problem of high THD in the current zero-crossing point of PFC converters and the impact of this problem on the circuit P.F. Section 3 describes the operation principle and the complete design of the PFC boost converter employed in this work. Section 4 presents the design technique of the proposed controlling circuits for the CCM-PFC converter based on the small signal stability modeling. Section 5 introduces the proposed AC and DC isolated voltage sensors for the economic and reliable operation of the digitally controlled PFC converters. Section 6 is the simulation of the complete designed converter with different control techniques. Section 7 is the conclusion and the future work. . Supply voltage-current waveforms for PFC-boost converter with conventional PI current controller.
In power system, THD value should be keep as low as possible, lower THD offer higher power factor, higher efficiency and lower current stress in power system components due to less peak currents. Usually, THD value should follow the standard specifications such as IEC61000-3-2 or IEEE 519-20142 for different classes of equipment.
Ignoring the effect of current distortion, the input P.F of the PFC converter can be expressed as (1).
where θvs is the voltage angle and θis is current angle for the input supply.
Equation (1) is not the fully definition of the converter P.F and usually this mathematical expression called as displacement factor (d.F). Power factor calculation using (1) can be applied only if the supply voltage and current waveforms are completely sinusoidal.
In most of power electronic circuits including the PFC boost converters, operation techniques and rapidly changes between on and off states of such these converters acts as nonlinear loads which can change the nature of the current so it's no longer to be sinusoidal waveform. Figure 2 shows the supply current and voltages of the PFC boost converter, which shows the current distortion when the boost converter switch changes rapidly from on to off states, this point usually called zero crossing point. The conventional control techniques using PI controllers can't fully remove the current distortion of the input current in the zero-crossing point due to the slow dynamic response of the current controller in this point [15], where the inductor current can't track the reference current when the supply current changes rapidly from the positive to negative value.
Root mean square value of the input current (Is_rms) for the PFC converter can be expressed as (2).
where Idc is the average current component, n represents the harmonic order, and when n=1, I1_rms is the fundamental component of the supply input current. With ideal voltage source which offer voltage only at the fundamental frequency (Vs_rms=V1_rms), the converter input average power (Pavg) can be calculated as (3).
Apparent power (S) which represents the supply active and reactive power components still include all of the current harmonics and can be expressed as (4). S = V s rms × I s rms = V 1_rms × √I dc 2 + ∑ I n_rms ∞ n=1 (4) From (3) and (4), the fully definition of PFC converter power factor with taken in account the current distortion can be expressed as (5).
where D.F represents the current distortion factor and equal to _ _ .
The THD value as relating to the current distortion factor can be expressed as (6).
So, the power factor (P.F) is the product of two factors called displacement factor (d.F) and distortion factor (D.F) as given in (5). The displacement factor (d.F) depends on the phase shift between the voltage and current of the input supply which is usually very low for the AC-DC power converters (less than 5 degree). And the distortion factor (D.F) which is depends on the total harmonic distortion of the current waveform.
For clear explanation of the relation between the P.F and THD in the PFC boost converters, for 5degree phase shift between supply voltage and current, to get P.F more than 99% as required by almost of the telecom power applications, THD must be less than 11.20 %.   to it is simplest design, reliability at higher power applications and economic price as compared with the other PFC topologies [1,12]. Boost converter unit consists of three main parts, the storage energy part which represents by inductor (Lb), the switching elements represents by high voltage switch (Qb), high-speed switching diode (Db), and the output filtering capacitor Cb.

Telecom AC-DC PFC Boost Converter operation principle and
The following section presents the operation principle and the design of the main components of the single-phase CCM-boost converter.  converter. When the switch (Qb) is closed as shown in Figure 4.a, the current will flow through the energy storage element (Lb) in the direction marked in the red dotted line, at this moment the energy will be storage in the inductor generating magnetic field, and when Qb is opened, as shown in Figure   4.b, the current circuit impedance will be increased leads to the current reducing, and the magnetic field previously created, will be reduced to maintain the current towards the load as marked also in the red dotted line. Thus, the polarity of the inductor voltage will be reversed, which make two sources in series causing a higher voltage to charge the capacitor (Cb) through the high-speed switching diode (Db).

Vin
The three parts of the boost converter should be optimally designed in order to maintain the circuit specified ripple currents, reduce the voltage stress in the switching elements during the converter operation and to maintain the output voltage with the specified ripple value required by the telecom applications.
PFC boost converter inductor (Lb) is designed based on the specified circuit ripple current (%Ripple) and the corresponding input and output voltage conditions [29]. PFC control circuits is usually designed to offer good performance with wide range of the input AC voltage (85-265) V, with using these specifications of the design, Lb value can be calculated as (7).
Also, the inductor maximum current (ILb Max) is determined based on the specified maximum current ripple [29] as expressed in (8).
where Vs min is the minimum supply voltage in root mean square (RMS) value, Vo is the rated output DC voltage, η is the converter designed efficiency, Po is the output rated power and Fsw is the switching frequency.
The output filter capacitor, usually called as the output bulk capacitor is designed to meet the specified output voltage ripple at the supply frequency requirements using (9).
where F is the input supply frequency, Vrpp is the output voltage ripple peak to peak value.
also, the Bulk output capacitor should be designed to offer the minimum voltage hold up with the specified time (thold) as expressed in (10).
The capacitor value is selected to have the larger value among the two equations.
Another important issue at the choosing of the output bulk capacitor, the capacitor series equivalent resistance (ESR) should be very low, which it is effects in circuit efficiency and the output voltage regulations. Also, higher ESR causes more ripple, influencing stability of the control loops [25]. Table 1 shows the designed specification and results for the 2500 W PFC boost converter employed in this work.

Design of the proposed PFC boost Converter Control systems
A block diagram of the complete schematic circuit of the telecom CCM-PFC converter including the digitally controlled technique is shown in Figure 5. CCM-PFC control circuit include two control loops implemented inside the DSP MCU as implemented in Figure 6, the outer voltage control loop and the inner current control loop.
The outer loop is used for regulating the output voltage (Vo) of the PFC converter to the reference value and also to generate the voltage error signal which is modified with the input sinusoidal voltage (Vin) to generate the reference current (Iref) value for the inner control loop as depicted in the control blocks in Figure 6. The inner loop is used to make the inductor current (ILb) track the refence current (Iref), inductor current is the DC value of the input supply current, so that any distortion in the inductor current will affect in the sinusoidal shape of the input supply current.  Usually the PI controller is enough to regulate the output voltage to the reference limit with good performance and fast response [14], so in the conventional and the proposed control circuits, the same PI controller has been used in the voltage control loop.

PFC Boost Converter Average Small Signal Modelling
For the PFC boost converter shown in Figure 3, the inductor voltage (VLb) can be expressed as (11).
The output capacitor current (ICb) can be expressed as (12).
where D refers to the converter duty cycle, Vo is the output bus voltage (Vo=Vbus), and R is the load resistance in ohm.
Assume all variables ( , , ) at the steady state values in the selected operational point( , , ) and small signal AC variation ( * , * , * * ) where: The PFC boost converter control circuit shown in Figure 6 should modify the duty cycle (D) based on the small signal AC variation to control the output voltage (Vo) and the inductor current (ILb).
Equations (14) and (15) can be re-written again as given in (16) and (17) with neglecting the term * * which it is the result of the product of two AC small signals.
Using the Laplace transform to get the small signal model, and arranging the model in state space matrixes form as given in (18). [ With using of the derived model of the PFC boost converter and selecting the appropriate system stability criterions which enhance the system stability and power quality improvement, the two control loops of the PFC boost converter can be designed as discuss in the following subsections.

Design of the Outer Voltage Loop
The design of the outer voltage control loop starts with obtaining the transfer function (T.F) of the outer voltage circuit by using the small signal stability modeling of the boost converter which describe the operation of the converter in the steady state operation point. For the boost converter shown in Figure 3.
Diode current is the sum of two components, load current ( ) and the output capacitor current ( ), which it can expressed as (25).
Applying the averaged small signal perturbation to (25) with the resistive load case give expression in (26).
With Comparing between the right-hand side parts of (24) and (26): So, the open loop T.F of the outer voltage system is given as (28). Figure 7 shows the control blocks for the outer voltage control loop of the PFC boost converter using the PI controller.  (29) where K Pv is the proportional gain, K Iv is the integral gain of the PI controller?
The closed loop T.F of the outer voltage control loop system (GCLV(s)) can be obtained as (30).
by substituting from (28) and (29) in (30) gives the closed loop T.F of the outer voltage control loop as expressed in (31).
So, the PI controller gains KPv, KIv can be designed using (31) and the standard form of the second order system T.F, by selecting the optimal stability criteria for the control system bandwidth and undamped natural frequency. Usually the bandwidth of the outer voltage loop must be very small to eliminate the harmonic of the DC-bus voltage reflected by the AC input voltage at 60 Hz [8].
In this work, the closed loop bandwidth of the outer voltage loop is assumed to be about Wn=85 rad/sec, the undamped natural frequency is about ξ=0.707, and for the reliable operation of the controller with the wide loading range, the PI controller parameters are sets to work with the minimum value of the load voltage Vo=320 V with the rated input supply voltage Vs=220 Vrms.
with using these values, the closed loop T.F of the outer voltage control loop finally can be expressed as (32).  Figure 8 shows the bode plot of the closed loop T.F of the outer voltage control loop, which shows that the controller offer unity gain for frequencies less than 27.8 Hz, this voltage control system working as a low pass filter helps to remove the 60 Hz voltage ripple. And the optimal PI controller T.F designed for the outer voltage control loop can be expressed as (33). In order to check the stability of the designed control voltage loop, root locus of the closed loop T.F was plotted as shown in Figure 9, which shows that the closed loop eigenvalues were located in the negative side of the pole zero plane, so the closed loop voltage system is inherently stable.

Design of the Inner Current Control Loop
Design procedure of the inner current control loop have been performed by the same way of the voltage controlling design and with an appropriate stability criterion for the inner current control loop. The inner current-control loop must have enough bandwidth higher than outer voltage loop bandwidth so that it be fast enough to track the current changes (to let the inductor current track the reference current), nevertheless, the current control loop bandwidth must be less than switching frequency (Fsw) to reject the noise at the switching frequency.
Using the small signal model of the boost converter obtained in (18), the open loop T.F of the inductor current control system Gi(s) can be expressed as (34).
From (35) it is observed that the stability of the inductor current system is depending on the converter duty cycle (D), in this work the PFC boost converter has been designed to obtain a constant output voltage with a wide range of the input voltage (85-265 Vac), based on these operating conditions, minimum duty cycle of the converter is considered about 0.40 and maximum duty cycle of about 0.95.
Before starting the design of the controller for the inner current control loop, the inductor current system stability checked with using Root locus stability plotted as shown in Figure 10 Figure 11 shows the bode plot of the Open loop of the inductor current system. Which it can notice that, the peak resonance frequency is proportionally with the duty cycle value, also the converter high bandwidth available with high duty cycle of the converter.   The T.F of the PI current controller (G PIi (s)) can be expressed as (37).
where KPi, KIi are the proportional and integral gains for the PI current controller respectively.
Since the converter switching frequency is selected about Fsw=100 kHz in this work, so for high frequency analysis, the capacitor can be shorted, and the open loop T.F of the inductor current system in (35) can be simplify as expressed in (38).
Substituting from (37) and (38) in (36), the closed loop T.F for the inner current control system can be derived as (39).
with using of the same converter operating conditions of the voltage and power which used in the voltage loop controller design and with high bandwidth of about 5000 rad/sec for the inner current control loop, the closed loop T.F of the inner current control loop can be expressed as (40).
G CLI (s) = (1.36 * 10 6 ) K Pi + (1.36 * 10 6 )K Ii 2 + (1.36 * 10 6 )K Pi + (1.36 * 10 6 )K Ii (40) Figure 13 shows the Bode plot of the closed loop T.F of the current control loop, which shows that the controller offer unity gain for frequencies less than 1610 Hz, this current control system working also as a low pass filter helps to remove the switching frequency noise.  Figure 14 shows that the eigenvalues of the closed loop current controller were located at the negative side of the pole zero plane, which ensures that the current control system has absolute stability. The IP controller characterized with high dynamic response, less overshoot as compared with the PI controller. So, an optimal IP controller has been proposed and designed in this section to replace the PI in the inner current control loop in order to eliminate the current distortion around the zero-crossing point. Figure 15 depicted the block diagram of the inner current control system with using the IP controller consisting of two control loops instead of one in case of the PI controller, where the integral gain feed in forward and the proportional gain feed backward.
The closed loop T.F of the inner current control loop using the IP controller can be expressed as (44).
The problem of the slow response of the inductor current to track the reference current can be solved by using the IP controller in the inner current control loop. Since, this controller structure provide two control loops for the current control system not only one as in case of the PI controller, which provide reliable and exact tracking of the inductor current to the reference current. Also, as shown in (44) there is no zero in the T.F using of the IP controller as compared with the T.F in (39) with the PI controller, which also provides system response with less overshoot.
To perform the comparative study between the PI and IP controllers based on the reliability to reduce the current distortion around the zero-crossing point, IP controller parameters were designed with the same operating condition and system stability criteria which used in the design of the PI controller. Therefore, the closed loop T.F of the inner current control loop with using the IP controller can be expressed as (45).
G CLI (s) = (1.36 * 10 6 )K Ii s 2 + (1.36 * 10 6 )K Pi s + (1.36 * 10 6 )K Ii (45) Figure 16 shows the Bode plot of the closed loop T.F of the current control loop with the IP controller, which shows that the controller offers unity gain for frequencies less than 823 Hz, this current control system with the IP controller also works as a low pass filter which helps to remove the switching frequency noise. Also, eigenvalues of the PI and IP controller are the same which shows that the closed loop T.F of the current controller with the IP controller is also stable as in case of the PI controller.  Figure 17 shows the bode plot of the closed loop T.F using the PI and IP controllers, which can notice that the overshoot using the PI controller was eliminated in case of the IP controller, also Figure  18 shows the step response with using the both controllers, overshoot of the current controller due to input step response was reduced from 21.7% with PI controller to 5.40% with using the proposed IP controller.  Step response of the inner current control loop with different controllers.

Design and Implementation of the Isolated voltage Sensors
As mentioned before in the introduction part, one of the disadvantages of the digitally controlled PFC converter is that the voltage and current sensors which required for the interfacing with the MCU is very expensive, in this section for economic and reliable operation of the designed digitally controlled PFC converter, two voltage sensors for sensing the AC input and the DC output voltage of the PFC converter were proposed to interface with the DSP TMS320F28335 from Texas instruments. Figure 19 shows the schematic circuit of the proposed isolated DC voltage sensor, For the DSP TMS320F28335 [31], the input voltage range to analog digital converter (ADC) range is 0 to 3 V DC voltage. So, the voltage sensors should be designed to convert the measured DC output voltage of the PFC converter to be in the available input range of the ADC of the DSP MCU. The proposed voltage sensor consists of two stages, the first stage is implemented using the voltage dividers R1, R2 and the isolation amplifier (IC1) to offer isolation between the high voltage power circuit and the low voltage control circuit. The second stage is the operational amplifier (IC2) circuit which used to adjust the sensor voltage to the required value based on its operation mode.
From the gain of the chosen isolation amplifier (IC1) in the first stage, the value of resistors R1 and R2 can be designed as (45).
where Vp_Max is the maximum primary voltage of the isolation amplifier and can be easily known from the datasheet of the chosen isolation amplifier (IC1), and then by choose the value of R1, the value of R2 can be easily calculated from (45). AMC1311 isolation amplifier from TI with primary voltage range about 2 V and unity voltage gain was used in the designed sensor which provides galvanic isolation up to 7 kV, low offset error, very low nonlinearity less than 0.03% with cheap price (about 3 $) which provide high reliability and economic design of the Isolated voltage sensing [32].
Operational amplifier should be chosen to offer wide bandwidth and low slew rate time and low noise. OPA320 operational amplifier from TI was used in this work with wide bandwidth more than 20 MHz and low slew rate time to the output voltage about 10V/us with cheap price (about 2.5 $) [33] and the expected total price of the proposed sensor will be not more than 10 $, this price is very cheap as compared with the other sensor types such as LV25-P sensor with price about 80 $ which used for the voltage sensing in reference [8].
The operational amplifier implemented in proposed sensor works in the inverting mode, so the closed loop voltage gain (β) can be expressed as (47).
where Vs_Max is the maximum secondary voltage of the isolation amplifier and can be calculated using (48).
where α is the isolation amplifier voltage gain.
with choose of R3 value, the value of the resistance R4 can be easily calculated from (47). Figure 20 shows the input output voltage curves for the designed isolated voltage sensor, which shows that for the input voltage of 400 V DC, the output voltage level is limited from 0 to 3 V with very small slew rate time about 25 us.  Figure 21 shows the schematic circuit of the proposed isolated AC voltage sensor. By the same steps of the DC voltage sensor design, the AC isolated voltage sensor has been designed and the offset voltage (Voffset) was used to remove the negative voltage part from the sensed voltage to be in the range of the DSP MCU input specification (0 to 3) V as shown in the waveform of the inputoutput waveforms in Figure 22.   Figure 23 shows the Complete schematic diagram of the CCM-PFC converter with the proposed digital control technique which simulated in the PSIM software. EMI filter was designed based on the design report of the 2.5 kW PFC analog converter from Infineon [ 29]. Digital control circuit of the PFC converter was implemented using DSP TMS320F28335 with DSP speed set at 150 MHz, and the switching frequency of the pulse width modulation (PWM) generator at 100 kHz. In all sceneries of the current loop control, the voltage loop control has been implemented using the PI controller.
At the rated input of (220 Vrms, 60 Hz), and full load condition of Po=2500 W, Vbus=400 V, Figure  24 shows the waveform of the inductor current (ILb) with the reference current (Iref) in case of PI current controller. From which we can clearly observe the distortion at the inductor current around the zero-crossing point due to that slow dynamic response of the PI controller around the zerocrossing point and the falling of the inductor current (ILb) to track the reference current (Iref). The distortion of the inductor current (ILb) at the zero-crossing point cause current distortion in the supply current (Isupply) as shown in Figure 25, which we can observe the zero-crossing distortion (ZCD) period is about 1.45 ms at the supply current. The ZCD effected in the sinusoidal shape of the supply current where the current waveforms can't follow the sinusoidal waveform of the supply voltage (Vsupply) as shown in the supply voltagecurrent waveforms in Figure 26.  At the rated input of (220 Vrms, 60 Hz), and full load condition of Po=2500 W, Vbus=400 V, IP digitally controller was applied on the inner current control loop in order to remove the distortion around the zero-crossing point. Figure 28 shows the waveform of the inductor current (ILb) with the reference current (Iref) in case of the PI current controller. From which we can clearly observe that the inductor current (ILb) can successfully track the reference current (Iref) and the ZCD was Significantly decreased.  Figure 29 shows Waveforms of the inductor and supply currents with the proposed IP current controller, which we can observe that the zero-crossing distortion (ZCD) period was decreased from 1.45 ms in case of PI controller to about 0.17 ms with using the proposed IP controller in the inner current control loop of the PFC boost converter.  Figure 30 shows the input supply voltage and current waveforms at full load condition and with using the proposed IP current controller, reduction of the ZCD period make the current waveform approximately sinusoidal shape and can follow the voltage waveform.  With different loading condition the performance of the designed PFC boost converter with different current control techniques was performed, Table 2 shows the PFC boost converter performance with loading conditions of (25%, 50%, 75%, and 100%) of the full load condition (2500 W). from the results, at full load condition the designed PFC boost converter with the proposed current controlling technique offer efficiency about 98.66 %, THD about 5.23 % and power factor about 99.93 %.

Conclusions and Future Work
Fast dynamic response IP current controller based on small signal stability modeling of the conventional PFC boost converter was proposed in this paper. Comparative analysis between using of the conventional PI and the proposed IP current controllers were also performed in this work which shows that inner current control loop of the PFC converter with the proposed IP controller reduced the THD around the zero-crossing point to about 5.23% at full load condition and offers PFC converter operation with power factor near to unity. Furthermore, two voltage sensors with economical price for the AC input and the DC output measurements of the digitally controlled PFC converter were proposed and used to interface with the DSP MCU TMS320F28335. The future plan will be focused in the experimental implementation and the design of the printed circuit board (PCB) of the digitally controlled PFC converter with the proposed IP current controller and isolated voltage sensors for the experimental performance investigation.