Design and Implementation of A New CFAR Based on Weighted and Statistical Algorithms

In the radar system, detection represents a basic and important stage in the receiver side. The detection process is based on the thresholding criteria; two philosophies of this criteria, constant and adaptive threshold. The constant threshold is simple in design, but it has a mis-detection and does not control the false alarm rate. As for the adaptive threshold, it is powerful in target detection, and better control of the false alarm rate, where it is called Constant False Alarm Rate (CFAR). Lots of research in the CFAR design, but the gap in the previous works is that there is no CFAR algorithm can be working with all or most environmental fields and all or most target situations. In this paper, The CFAR, which can work with the most environment and most of the target situations, has been presented. The producing the design and implementation of the new practical CFAR processor is presented. Where, the new CFAR is a combination of the properties of three different CFAR algorithm (CA, OSGO, and OSSO), and from two different families; averaging and statistical. Where it has overperformed of it's PD is 97.25% for simulation and 96.25% for the implementable version for different target situations. The simulation analysis is made by using Matlab 2015, while the implementation is done by using Xilinx Spartan 700 3a.

So as to save the false alarm constant, a threshold level is calculated, and target detection is performed depending on this level. If a target echo passes this level, a target declaration is made, if noise or clutter return or both pass this level false alarm is occurring.
The threshold level setting of the CFAR detector should follow the background noise power that is estimated by an algorithm depends on the detection environments. Targets should be detected in different detection environments. These environments are homogenous environment (single target or multi-targets) and non-homogeneous environment (closed multi-targets or clutter edge).
Corresponding to these environments various CFAR detector had been developed, namely, Cell Averaging CFAR (CA-CFAR) [1], Greatest Of (GO-CFAR) [2], Smallest Of ( SO-CFAR), Ordered Statistic ( OS-CFAR) [3]. In addition, the combination of different CFAR algorithms were proposed such as Trimmed Mean CFAR (TM-CFAR) [4], Order Statistic Greatest Of (OSGO-CFAR) [5], Order Statistic Smallest Of (OSSO-CFAR), and Variability Index CFAR (VI-CFAR) ), fusion of different CFAR detectors such as (AND-CFAR) and (OR-CFAR) detector [6]. Also, [7] present CA-clutter map (CM-CFAR), but it affected by interfering. Then solve this problem by order statistic clutter map CFAR (OSCM-CFAR). A mean of order statistics and cell averaging" (MOSCA) CFAR was presented by [8] for Swirling II target environmental. A Forward Automatic Order Selection Ordered Statistics Detector (FAOSOSD) for an estimate the interfering target was presented by [9]. A switching CFAR (S-CFAR), is presented in [10] to operate in a homogeneous environment and multiple targets with clutter transition situations. A 2D with optimize the computational time CFAR was proposed by [11]. A combination of cell-averaging and trimmedmean a proposed CATM-CFAR was presented by [12] to detect targets in Weibull clutter. In order to mitigate the performance degradation in non-homogeneous Weibull clutter environment, a constant false alarm rate detector based on the skewness (SK) and mean ratio (MR) named SKMR-CFAR is proposed by [13]. [14], to guarantee the continuity of detector performance with different field environments and target situations based on a neural network (NN) proposed a Closed Loop CFAR (CL-CFAR) processor. Therefore, to fill the gap in the previous works and with a simple and inexpensive detector, this paper presents a Statistical Weighted (SW) CFAR, which is designed and implemented, with FPGA to detect the targets with different environments, which is based on the properties of their CFARs not on CFARs itself.

Proposed SW CFAR
As it is known, none of the elementary CFAR detectors are the best and suitable for all detection environments (single target, multi-targets, closed multi-targets and clutter edge). The idea of the proposed SW CFAR is to make a combination of these elements CFAR detectors to get a detector able to operate with high performance in most of the detection environments.

Architecture of the Proposed SW CFAR
The architecture of the proposed CFAR is the combination of properties of the mean level and ordering families and as follows: the CA-CFAR and Weighted-CFAR are from mean family and OSSO-CFAR and OSGO-CFAR from statistical family.
The operation of the proposed CFAR is starting when the return signal reaches to the last cell in the leading window. Then sorting the content of the leading and the lagging windows ascending. After that, take 3/4 of the content of the windows, and apply the algorithm to the selected cells of leading and lagging windows. The threshold will be extracted after weighting it by α, β, and then the decision can be made as shown in the Fig. (1). This means, that the clutter, power is estimated by applying the principle of OSGO to the leading and lagging window of SW CFAR, while, the OSSO principle was applied to the leading and lagging window over weighted them by the factor (α) and (β).
Therefore the main operations of the introduces CFAR are the sorting of windows contents and weighting of the sorting output. According to this procedure the CFAR is named

Derivation of PD and Pfa of SW-CFAR
The derivation is based on the consideration the received noise is distributed as Gaussian; while the envelope of detection signal is distributed as Rayleigh. Therefore, the Hypothesis testing model is derived as follows [15]; = 1+ λ, and λ is SNR (dB).
The reference random variable xi (i = l, . . . , n), yj (j= 1, . . . , 2n) the reference cell is taken to be homogenous with general PDF; Their common cumulative distribution function (CDF) is evaluated as; For CFAR detector applying the above decision rule, V and Z are independent random variables.
Therefore, the detection probability of CFAR detector in homogenous background is Independent random variables V and Z are used for the CFAR detector to make decission. The probability of detection of CFAR detector in (IID) environment is; Where; ( ) -the moment generating function of Z. It's defined as then the is; The probability of false alarm is; The probability of detection for SW-CFAR is; while, the the probabilty of false alarm for SW-CFAR is;

3-Simulation results of the Proposed SW-CFAR
The performance of the SW-CFAR processor is evaluated for the homogenous and nonhomogenous environment in four target situations (single, multi-target, closed multi-target and clutter edge) separately and with other CFAR algorithms for comparison. The performance of the SW CFAR is comparable to the performance of CA-CFAR and TM-CFAR. However, it is better than other CFAR families. As shown from Fig.(3), the performance of SW CFAR is very good as other family in the case of multi targets. Its performance is comparable to the performance of the OSGO-CFAR. From the previous works, it is shown that the OSSO-CFAR detector is the best for detection of closed multi-targets. However, the proposed SW CFAR has better performance for detection of closed multi-targets than OSSO-CFAR according to Fig. (4) 5) show that the SW-CFAR has a comparable performance to OSSO CFAR for target detection in clutter edge. The result indicated that the SW-CFAR has a highest Pd compared with other CFAR detectors.

4-Hardware Implementation of the Proposed SW-CFAR
According to the suggested SW-CFAR results that has the best performance, the FPGA design of this CFAR is built as shown in Fig. (7-a)   Generator and the simulation is done by MATLAB-Simulink related with "XGS".
The hardware platform used to implement the proposed SW-CFAR is Spartan-3A DSP 3400A.
Corresponding to available hardware characteristics, there are several limitations in FPGA design, these are; 1. The treatment received signals length at each clock is 33 symbols, where sixteen symbols for each window (leading and lagging) and one symbol for CUT.
2. The number of bits that represent the symbol is 8 bits. Also, a fixed-point precision of 8 bits.

FPGA implementation of subsystems
There are many subsystems implemented by FPGA, these are;

1-Shift register and sorting:
The received signal is generated in the computer by Matlab, and then entered to the FPGA. The first subsystem is the shift register and sorting. The signal will be shifted to the leading window through the CUT cell and lagging window. After that, the content of leading and lagging window will be sorted in ascending order individually. Fig. (9) shows this subsystem. To sort the input signal by ascending rank without employing RAM, the online sorting method is suggested for implementing this procedure. This process is utilized to give a greater

2-Select the 12th bin subsystem.
The proposed design is based on select 3/4 of the windows, this means 12 bins. In the sorting ascending process means, the maximum is bin 12. Therefore, this subsystem selects the bin 12 from leading and lagging windows.

3-Select MAX and MIN subsystem.
These subsystems select the maximum and minimum values between the two maximum and minimum from the sorting, leading and lagging (bins 12th).

4-Adder and weighting subsystem
This subsystem is used for weighting by (0.5 and 0.75) which represented alpha and beta weighted factors respectively, then add the results of the above subsystems.

6-Plotting I/O subsystem
This subsystem is content many blocks to plot the input and output of the proposed CFAR.

Platform
There are four steps to complete the design flow of FPGA; 'design entry', 'design synthesis', 'design implementation', and 'Xilinx device programming'. The buildings of the suggested scheme, including the written of its VHDL files and use a block from the library are done in a first step.
Code of VHDL and block are syntax checks and the design hierarchy study is done in a second step to enhance the proposed design scheme for FPGA architecture. The third step is accountable for linking input netlists and bonds within design file by 'Translate' process, fit the design system to FPGA hardware device's resources through 'Map' process. Finally, place and route the design system within the timing bonds by 'Place and Route' process. The final step creates the bitstream file to the design system so as in order to download to the FPGA platform.
More of the limitations of suggested design relate to the inadequate Xilinx device's presented resources that were checked and operated in the map process. The Map process of SW-CFAR and overview of the design of line are presented in Fig. (10).
a) The device utilization summary SW-CFAR system.
b) The power consumed in the FPGA kit  The hardware platform interface is either Ethernet cable or JTAG, this depends on the accessibility of those cables. In this paper, the Ethernet cable with point-to-point link is utilized to construct the SW-CFAR on FPGA platform. Fig. (7) shows this connection. An Ethernet cable provides a high throughput link with the FPGA platform and present best bandwidth when used in the applications of real life.
The host computer connects with the Spartan-3A DSP 3400A board in order to implement the SW-CFAR detector, figure (7) shows this action.

SW-CFAR Hardware Result
The similar conditions, which have processed in simulation for measuring the detection performance of SW-CFAR proposed, are processed to estimate the hardware implementation success rate. The return signal is generated by using MATLAB and it is sent by Ethernet cable to the FPGA device. Distinct levels from (5 dB to -5 dB) of AWGN were added to The generated signals . Each tested signal contains of 33 (32 for leading and lagging window and one for CUT) symbols generated randomly and repeated many times in the screen window for different target's situation and locations. Each figures from (11) to (15) consists of three parts ; the first part represents the received signal and adaptive threshold, while the second part shows the decision results and the third art appears the clock pulse, which the process begins and continues with it.
For all the Figs of all target's situation, the first figure, it is clear the beginning of the process to create the threshold is not correct, because of the leading window of the CFAR is filled by zero values and not real values. Therefore, the created adaptive threshold is not correct, then the decision is an error. For this reason, the decision process is beginning after the leading window is full by the received signal.

Single Target
Three cases for single target are considered, each one with different locations. One of these cases is shown in Fig. (11), which the target is located at bin 13. It is clear from the Fig. (11-a) of that the adaptive threshold follows the change in cells value. Also, from the Fig. (11-b) the decision is correctly at the location of the target at bin13. In the second case, a single target is considered at bin 2. The target is detected at bin 2 and two false alarms at bin 3 & 4. In this context, in the third case, a single target is considered at bin 17 In all cases the detector is take a correct decision at the target locations.

Multi-targets
In the first experiment of multi-target detection, three targets are considered at bins 13, 23 & 32 as in Fig.(12). From the second part of the Fig. (12), it is clear the overperfom of the SW CFAR and the three targets are detected at cottect locations.

Close Multi-Targets
The first experiment for closed multi-targets is shown in Fig.(14) where the targets at bins 3,6,8.The second part of Fig.(14) shows that these targets are detected in correct locations.

Clutter edge
Target detection in clutter edge is one of the important situation of the real detection environment.
Three experiments are done to examine the performance of the SW CFAR in the clutter edge environment. In the first experiment, the clutter is in bins 1,2,3,5,6, while the target at bin 4 as shown in Fig. (15). The summarization of the results of the SW-CFAR are presented in Table (1), where this table appears the probability of detection of many algorithms and the SW-CFAR for comparison. • The first point is that the advancement of the detection in simulation and implementation with an acceptable probability of detection.
• While the second point is that the SW-CFAR does not fluctuate in detection with different target situations. Conversely are the other CFAR algorithms.

5-Conclusion
The CFAR is a technique being used in detection process stage to keep the false alarm at an acceptable level. There are many CFAR algorithms that can be used, each one is used with certain environment, while no CFAR can work in all environments. The received signal properties is changed according to the situations of the detected targets. There are four target situations; Single, multi-target, close multi-targets, and targets with clutter edge. There is a suitable CFAR algorithm with each target's situation, but, this CFAR is a degradation with other target's situations.
Therefore, the real problem is, the target needs to be detected is always in motion, then it's situation is changed. Therefore, the CFAR which can be operated with all target situations or with most of it must be built.
Accordingly, this paper presents a SW-CFAR algorithm; which enhance the detection of the radar system to solve the above problem.
From the evaluation and simulation the proposed new SW-CFAR many concluded points, where the combination of the CFAR properties outperforms the combination of the CFAR nether it is families as in the proposed CFAR processor. Where, this CFAR offers a good performance in all radar environments compared with other detectors, with less complexity in FPGA implementation and the highest probability of detection. In this context, the average PD which has gained 97.25% with a range of (Pfa) from 10 −4 to 10 −6 for simulation and 96.25% with same range of (Pfa) for Based on the obtained results in this paper, several points have been noticed to be trying to satisfy the goal as a future work. These points; Other CFAR (properties) combination may give over performance in detection. Also, can Built the CFAR processor by using NN in optimal with all environments and all target situations. To enhance the detection performance, can design a CFAR based on frequency Doppler signature. Implement the proposed CFAR with another version of FPGA kits or TMS for improving their performance according to the speed and complexity.