Preprint Concept Paper Version 1 Preserved in Portico This version is not peer-reviewed

Soft-Core Architecture for Odd/Even Order Sampling I/Q Demodulator with Dual-Port Block Memory Considerations

Version 1 : Received: 31 August 2019 / Approved: 1 September 2019 / Online: 1 September 2019 (14:40:07 CEST)

How to cite: Mfana, M.; Hasan, A.N. Soft-Core Architecture for Odd/Even Order Sampling I/Q Demodulator with Dual-Port Block Memory Considerations. Preprints 2019, 2019090014. https://doi.org/10.20944/preprints201909.0014.v1 Mfana, M.; Hasan, A.N. Soft-Core Architecture for Odd/Even Order Sampling I/Q Demodulator with Dual-Port Block Memory Considerations. Preprints 2019, 2019090014. https://doi.org/10.20944/preprints201909.0014.v1

Abstract

Soft-Core architecture for Analogue to Digital Converter (ADC) sampling is useful for mixed signal applications. Soft-core architecture for cutting edge odd or even ADC sampling with interface to block RAM memory has not been found. Soft-core architecture as a concept has become popular due to the advantage of customization for different applications as compared to general-core architecture suited for single application. The latest generation of piece wise sampling is odd sampling and was introduced in the second decade of the 20th century. Odd and even order sampling techniques are analogue in nature driven by a tuned (tuned for odd or even) mixer. This paper proposes a third-generation piece wise sampling with soft-core architecture that enables an option to select both odd and even while interfacing to memory mapping. The proposed odd/even has superior SNR performance of 6 dB as compared to existing architecture such as Mod-∆ which recorded worst performance of 18 dB. Advances in soft-core technology have allowed a niche odd/even switching field to be identified and studied, the study has also been extended to include memory architecture.

Keywords

soft-core architecture; system on chip (SoC); radio frequency system on chip (RFSoC); adaptive compute acceleration platform (ACAP); scalar processing; vector processing; I/Q demodulator; odd order sampling; even order sampling; analogue to digital converter (ADC)

Subject

Engineering, Electrical and Electronic Engineering

Comments (0)

Comment 1
Received: 8 September 2019
Commenter: Vadym Slyusar
The commenter has declared there is no conflict of interests.
Comment: Dear Madodana Mfana and Ali N. Hasan,

Thank you for your preprint and your citations of my publication.

I'm sorry, but your preprint has some mistakes regarding my results. Please update your text with use my next comments:
1) In row Number 182 you wrote " and V. I. Slyusar et al [1] applied ". In reallity I don't have co-authors of this publication, You should be write here and in rows No. 200 and 202 only " and V. I. Slyusar [1] applied "

2) In rows No. 184 you wrote: "implements a 4 order FIR filter instead of a 7 order FIR filter." Please change It to
"implements a 7 order FIR filter instead of a 8 order FIR filter."
Also please update tables 1 and 2 for 7 order FIR filter with different coefficients from my Publication.

3) In rows No. 203 - 205 you wrote: "V. I. Slyusar et al [1] also introduces us to the idea of odd order sampling which is developed from even order sampling in [2], although limited theory derivation of odd order sampling he was able to apply it to single channel ADC I/Q sampling which uses 3rd order FIR filtering. "

Please update this sentence, because in my publication I considered not only 3rd order FIR filtering, but also 5th order (Eduation (12)), 7th order (Equation (19) and Table 1), 9th order (Eq. (21),(23)) and 11th oder (Eq. (25)). It is very importent.

4) In rows No. 207 and 213 please change "7 samples" to "8 samples" , because you use 8 samples with samples Nu. Zero.

Thank you for your understanding.
Best regrads,
Vadym Slyusar
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