Role of MOSFETs Transconductance Parameters and Threshold Voltage in CMOS Inverter Behavior in DC Mode

The objective of this paper is to research the impact of electrical and physical parameters that characterize the complementary MOSFET transistors (NMOS and PMOS transistors) in the CMOS inverter for static mode of operation. In addition to this, the paper also aims at exploring the directives that are to be followed during the design phase of the CMOS inverters that enable designers to design the CMOS inverters with the best possible performance, depending on operation conditions. The CMOS inverter designed with the best possible features also enables the designing of the CMOS logic circuits with the best possible performance, according to the operation conditions and designers’ requirements.


Introduction
CMOS logic circuits represent the family of logic circuits which are the most popular technology for the implementation of digital circuits, or digital systems.The small dimensions, low power of dissipation and ease of fabrication enable extremely high levels of integration (or circuits packing densities) in digital systems [1][2][3][4][5].
By noise margins, CMOS technology is the dominant of all the IC technologies available for digital circuits design.The fundamental circuit of CMOS logic circuit is the CMOS inverter.Electrical and physical parameters that characterize the complementary MOS transistors (or complementary MOSFET transistors) determine the behavior of CMOS inverter, as for static conditions of operation, as well as dynamic conditions of operation [6][7][8][9].
The CMOS inverter consists of two complementary MOS transistors (of an enhancement-type NMOS transistor and an enhancement-type PMOS transistor, because the enhancement-type of MOSFETs have high performance on depletion-type of MOSFETs), interconnected as in Figure 1 [6,10].
The NMOS transistor is called pull-down transistor, while the PMOS transistor is called pull-up transistor [11].Complementary MOS transistors in the CMOS inverter operates in complementary mode depending on voltage level applied to the input terminal (to the gates of MOS transistors).In the CMOS inverter, the contribution of both MOS transistors is equal to the circuit operation characteristics, therefore both transistors are considered as driver transistors.By circuit topology for input high voltage (high level), the NMOS transistor drives (pulls down) the output node while the PMOS transistor acts as the load (nonlinear resistor), and for input low voltage (low level) the PMOS transistor drives (pulls up) the output node while the NMOS acts as load [6,7,12].

The role of the complementary MOSFET (NMOS and PMOS) transistors parameters in characteristic properties of the CMOS inverters
The behavior of the CMOS inverter for static conditions of operation is described by the voltage transfer characteristic (VTC), and for dynamic operation conditions is described by the time response during switching conductions [6,7].The typical VTC characteristic of the CMOS inverter is shown as in Figure 2. In the CMOS inverter, the NMOS transistor and PMOS transistor can be treated as a switch which operates in complementary mode [12].
For construction of the VTC characteristic of the CMOS inverter, five different combinations of operation modes of the NMOS and PMOS transistors should be examined, which are the results of the various ratios of the input voltage levels and the output voltage levels.Operation modes of complementary MOS transistors within particular regions of the VTC characteristic are presented in Table 1.The characteristic properties that characterize the VTC characteristic are some voltage critical values at the input and output terminal of the CMOS inverter, as: VOH, VOL, VIL, VIH, Vth [3], [4].

Region Vin Vo
VOH -output high voltage when output level is a logic "1" (high logic level), VOL -output low voltage when output level is a logic "0" (low logic level), VIL -maximum input voltage which can be interpreted as a logic "0", VIL -minimum input voltage which can be interpreted as a logic "1".
The voltage critical values at input and output of the CMOS inverter are determined by using combinations of operation regions (operation modes) of the NMOS transistor and the PMOS transistor, depending on the level of the output voltage values relative to the voltage values at the input of the CMOS inverter.
The critical value of output voltage VOH can be calculated by using the A region of VTC's, when the NMOS transistor operates in the cut-off mode, while the PMOS transistor operates in the linear mode, and after calculation will have voltage level of: when VDD -power supply voltage (source voltage).
By using the B region of the VTC characteristic, the definition for VIL critical value (the smaller of the two input voltage value at which the slope of the VTC characteristic becomes dVo/dVin= -1) and the operation modes of complementary MOS transistors according to Tab.The body effect of NMOS and PMOS transistor is not present in the CMOS inverter, because VSB of both transistors is zero.This will have to be taken into consideration in other types of MOS inverters, as in NMOS inverter, when it will influence the threshold voltage of NMOS and PMOS transistors, as well as the VTC shape of inverters.Also, by using the definition for obtaining the expression for input voltage critical value VIH (the larger of the two input voltage values at which the slope of the VTC characteristic becomes dVo/dVin = -1), and by using D region in VTC characteristic of CMOS inverter, and operation modes of the NMOS, and the PMOS transistors according to Table 1, we can obtain the expressions for the critical voltage value VIH and the output voltage Vo, as: In the CMOS inverter, it is also important to consider an electrical parameter which represents the threshold voltage of the CMOS inverter Vth, which is calculated under the condition that Vo = Vin.
For calculation of the threshold voltage of CMOS inverter Vth, the C region of VTC characteristic is used, where both transistors (NMOS and PMOS devices) operate in saturation mode and will have: The low output critical voltage value VOL is calculated using the E region of VTC characteristic, when the NMOS transistor operates in linear mode and the PMOS transistor operates in cut-off mode, resulting in: The critical input and output voltage values are also determinative to the noise margins values which characterize CMOS inverter for two logic levels (NML and NMH) in static condition of operation (steady state).The noise margins for two logic levels are expressed as: Relaying on fabrication processes advances of MOS transistors, it is possible that electrical and physical parameters which characterize MOS transistors can be controlled during fabrication process [1,3,6].Therefore, we will examine the impact of these parameters on the particular magnitudes that characterize the CMOS inverter and based on them, can be defined the routes which lead to the design of the CMOS inverter with favorable performance according to the operation conditions and digital circuits based on CMOS logic [1,9,[15][16][17].

Results and Discussion
The dependence of the input voltage critical value VIL on the ratio of MOS transistors tranconductance parameters for two different values of the threshold voltage of NMOS driver transistor, when the value of the PMOS transistor threshold voltage (PMOS can be treated as a load) remains constant, is presented in Figure 3.  From the results presented in Figures 3 and 4 for the input voltage critical value VIL, we note that as the higher the value of the transconductance parameter ratio of complementary MOS transistors is, the low critical value of input voltage VIL will decrease.For higher values of the NMOS threshold voltage, the input voltage critical value VIL, will shift to higher values.Also, for the higher value of the absolute value of PMOS transistor threshold voltage, the input voltage critical value VIL will shift to the lower values.
The results presented in Figure 5 show that when the MOS transconductance parameters ratio have higher value, the output voltage value Vo will have higher values, when the input terminal is biased by Vin = VIL (or by input low voltage critical value).Also, the impact on output voltage value Vo will have likewise the values of MOS transistors threshold voltage, but this impact is less important compared to the ratio of MOS transistors transconductance parameters.However for lower values of the complementary MOS transconductace parameters ratio, the impact of threshold voltage of complementary MOS transistors will be more significant.Based on the obtained results, it is shown that the higher value of MOS transconductane parameters ratio is, the CMOS threshold voltage value will be decreased, respectively, it will be shifted towards the logical lower value.For higher values of the NMOS threshold voltage, the value of the CMOS threshold voltage Vth would increase in value, especially the impact will be more prominent for greater values of the transconductance parameters ratio kr (kn > kp).While when the threshold voltage of the PMOS transistor has a higher value by absolute value, the value of the CMOS threshold voltage Vth will be decreased, and this decreasing will be more significant when the transconductance parameter ratio kr has lower values (kp < kn).
The immunity of CMOS inverter on unwanted signals is expressed through the noise margins for both logical levels (for low level and for high level).The parameters that characterize the  The results in Figure 10 indicate that the higher values of the MOS transconductance parameters ratio kr, noise margin for the low level will be lower.For the lower value of the NMOS transistor threshold voltage (Vt0,n), the level of noise margins NML (noise margins for low level) will decrease, resulting in the significant reduction in the band of higher values of the transconductance parameter ratio kr.Also, the smaller the PMOS transistor threshold voltage value (Vt0, p) by absolute value, the level of noise margins NML (noise margins for low level) will increase, especially in the range of small values of the transconductance parameters ratio kr.The level of noise margins NMH (noise margins for high level) will increase when the MOS transconductance parameter ratio is designed to be higher, Figure 11.For smaller value of NMOS threshold voltage, the noise margin for high level NMH will increase especially in the range of higher values of the transconductance parameter kr.While the lower value of PMOS threshold voltage by absolute value (Vt0,p), the level of noise margins NMH will decrease, especially with significant impact in the range of low values of the transconductane parameter ratio kr.

Preprints
By matching the values of complementary MOS transconductance parameters and values of their threshold voltage, the CMOS inverter can be designed with higher performance, depending on the requirements of designer that dictate operation conditions.For CMOS inverter with matched parameters as: kn = kp and Vt0, n =| Vt0, p | will be achieved that the noise margin to be equal to both logic levels and the value of the threshold voltage of the CMOS inverter will be half of voltage source Vth = VDD/2.The CMOS inverter which possesses these features is called symmetric inverter and it must satisfy the condition: (11) and although the MOS transistors built by equal length of channel defined by lithographic process, it appears that: The behavior of CMOS inverter is described through the VTC in DC mode of operations (steady state mode).The parameters that characterize the complementary MOS transistors influence in the shape of the VTC characteristic.At the design phase of CMOS inverter, the requirements of CMOS inverter behavior are presented, so the task of the designer is to adjust the parameters of the NMOS and PMOS transistors as much as possible, which enable the design of the CMOS inverter with acceptable performance.The impact of NMOS and PMOS transistor parameters in shape of the VTC characteristic is shown in Figure 12.For the higher values of complementary MOS transistors transconductance parameters ratio (kr), lower value of the NMOS transistor threshold voltage (Vt0,n) and higher value by absolute value of the PMOS transistor threshold voltage (Vt0.p), the input voltage critical value VIH will decrease, whereas noise margin for high level NMH will increase.
As for the output voltage value Vo when Vin = VIL, for the higher values of complementary MOS transistors transconductance parameters ratio (kr), lower value of the NMOS transistor threshold voltage (Vt0,n) and higher

Figure 1 .
Figure 1.The structure of the CMOS inverter which contains two complementary enhancement-type MOS transistors.

Figure 2 .
Figure 2. The typical VTC of the CMOS inverter.
-the threshold voltage of the NMOS transistor, Vt0,p -the threshold voltage of the PMOS transistor, kr -the transconductance parameters ratio of the NMOS and the PMOS transistors, Vin -input voltage.
kn -transconductance parameter of the NMOS transistor, kp -tranconductance parameter of the PMOS transistor, ' n k -process transconductance parameter of the NMOS transistor, ' p k -process transconductance parameter of the PMOS transistor, W -channel width of the MOS transistor, L -channel length of the MOS transistor, whereas indexes n and p indicate the NMOS and PMOS transistor.

10 )
From the expressions of the input voltage critical values (VIL and VIH) and the output voltage critical values (VOL, VOH) achieved above, impact on these characteristic voltage values will have: the values of the power supply voltage (source voltage), the values of the threshold voltage of the complementary MOS transistors, as well as the values of transconductance parameters which characterize the complementary MOS transistors.

PreprintsFigure 3 .
Figure 3.The dependence of input voltage critical value VIL on ratio of MOS transistor transconductance parameters (the ratio of NMOS transconductance parameters on PMOS transconductance parameters) kr for two different values of NMOS threshold voltage (Vt0,n), when threshold voltage of PMOS transistor has a constant value of Vt0,p = -0.5V.

Figure 4 . 5 .Figure 5 .
Figure 4.The dependence of input voltage critical value VIL on the ratio of MOS transistor transconductance parameters kr for two different values of PMOS threshold voltage (Vt0,p), when threshold voltage of NMOS transistor has constant value of Vt0,n = 0.5V.

Figure 6 .
Figure 6.The dependence of the voltage critical value VIH on MOS transistors transconductance parameters ratio kr for two parametric values of NMOS transistor threshold voltage, when PMOS transistor threshold voltage remains constant Vt0,p = -0.5 V.

Figure 7 .
Figure 7.The dependence of voltage critical value VIH on MOS transistors transconductance parameters ratio kr for two parametric values of PMOS transistor threshold voltage, when NMOS transistor threshold voltage remains constant Vt0,n = 0.5V.

Figure 8 .
Figure 8.The impact of the transconductance parameters ratio (kr) of MOS transistors (NMOS and PMOS) on value of the CMOS inverter threshold voltage (on value of CMOS inverter switching threshold voltage) for two different values of the NMOS threshold voltage, when Vt0,p = -0.5 V and source voltage VDD = 2.5 V.

Figure 9 .
Figure 9.The impact of the transconductance parameters ratio (kr) of MOS transistors (NMOS and PMOS) on value of the CMOS inverter threshold voltage Vth (on value of CMOS inverter switching threshold voltage) for two different values of the PMOS threshold voltage, when Vt0,n = 0.5V and VDD = 2.5 V.

Preprints
(www.preprints.org)| NOT PEER-REVIEWED | Posted: 28 July 2017 doi:10.20944/preprints201707.0084.v1 complementary MOS transistors in a CMOS inverter determine the noise margins level for both logical levels.The dependence of noise margins (NM) on the complementary MOS transistors transconductance parameters ratio, for several parametric values of MOS transistors threshold voltages in both logic levels are shown in Figures 10 and 11.

Figure 10 .
Figure 10.The dependence of the noise margins for low logic level NML on complementary MOS transistors transconductance parameters ratio kr, for three cases of different MOS transistor threshold voltage (NMOS and PMOS transistors), when VDD = 2.5 V.

Figure 11 .
Figure 11.The dependence of the noise margins for high logic level NMH on complementary MOS transistors transconductance parameters ratio kr, for three cases of different MOS transistor threshold voltage (NMOS and PMOS transistors), when VDD = 2.5 V.

Figure 13 .
Figure 13.The impact of the NMOS transistor threshold voltage (Vt0,n) on VTC shape, when PMOS transistor threshold voltage is Vt0,p = -0.5V,and transistors have identical dimensions.

Figure 14 .
Figure 14.The impact of PMOS transistor threshold voltage (Vt0,p) on CMOS inverter VTC shape, when NMOS transistor threshold voltage value is Vt0,n = 0.5 V, and transistors have identical dimensions.

Table 1 .
Operation modes of complementary MOS transistors (NMOS and PMOS transistors)