A 14-bit Hybrid Incremental Sigma-Delta / Cyclic ADC for X-ray Linear Array Sensor

Yuze Niu 1,2, Yacong Zhang 1,2,*, Zhuo Zhang 1,2, Miaomiao Fan 1, Wengao Lu 1,2 and Zhongjian Chen 1,2 1 Key Laboratory of Microelectronic Devices and Circuits, Department of Microelectronics, Peking University, Beijing 100871, China; yzniu@pku.edu.cn (Y.N.); zhangzhuo1658@163.com (Z.Z.); mayunfmm@163.com (M.F.); wglu@pku.edu.cn (W.L.); chenzj@pku.edu.cn (Z.C.) 2 Peking University Information Technology Institute (Tianjin Binhai), Tianjin 300452, China * Correspondence: zhangyc@pku.edu.cn


INTRODUCTION
X-ray imaging system is widely used in many fields such as medical, industrial, and safety monitoring areas [1].Readout Integrated Circuit (ROIC) of the X-ray sensor has a significant effect on signal-to-noise ratio of the system [2].Since digital signal has strong resistance to interference, ROIC integrated with Analog-to-Digital Converter (ADC) is drawing more and more attention.There are many channels in the ROIC of X-ray linear array sensor, and it is a good choice to integrate an ADC in each channel to alleviate speed requirements for ADC.The architecture of the ROIC is shown in Fig. 1.The front-end circuit of the ROIC is called Capacitive Trans-Impedance Amplifier (CTIA), which is used to convert tiny current signal generated by the X-ray linear array sensor to analog voltage signal.The ADC in each channel of the ROIC should feature small die area, low power consumption, high resolution and moderate speed to realize good performance.conversion speed too slow to meet the requirement [3][4].Although high order Σ-Δ ADC can improve conversion speed to a certain extent, the complexity of the filter is increased accordingly, which leading to important die area and power consumption [5].Cyclic ADC and Successive approximation register (SAR) ADC need only N clock cycles for N bits conversion, but Cyclic ADC leads to limited accuracy and high accuracy SAR ADC occupies large die area [6][7].Hybrid incremental Σ-Δ/cyclic ADC is presented to overcome the disadvantages [8].Incremental Σ-Δ ADC acts as the first stage to achieve high resolution and cyclic ADC is the second stage to shorten conversion time.
In this paper, a new incremental Σ-Δ/cyclic ADC structure based on pseudo-differential OTA is presented.The two stages share the same hardware, and each ADC adopts the redundant signed digit (RSD) principle for a large tolerance of comparator offset.The pseudo-differential structure is used to decrease power consumption, and increase the voltage swing range.The CMFB circuit can suppress the effect of charge injection, and guarantee high conversion resolution.This hybrid ADC compromises speed and accuracy with small area and power consumption, which is suitable to be integrated in channel.This paper is organized as follows.Section II describes the architecture and principle of the presented ADC.Section III shows the design consideration of circuit.Section IV provides the experimental results of a fabricated prototype.Finally, Section V concludes this paper.

II. ARCHITECTURE AND PRINCIPLE
A. Architecture of Hybrid ADC Fig. 2 shows the architecture of the presented two-stage hybrid ADC.The incremental Σ-Δ ADC, as the first stage, produces a serial digital bit stream and the residue voltage res V .The bit stream is translated into N-bit MSBs by a digital lowpass filter.The residue voltage is passed on to the second stage ADC (i.e.cyclic ADC) to obtain M-bit LSBs.The LSBs and MSBs are connected by the data connection module which costs 1-bit resolution to output the final (M+N-1)-bit digital signal.Σ-Δ ADC and cyclic ADC use the same integrator, 1.5-bit ADC and 1.5-bit DAC to perform conversion.Both stages adopt RSD algorithm to avoid the influence of comparator inaccuracy [9].
For the incremental Σ-Δ ADC, it takes 2 N clock cycles for N-bit resolution.For each cycle, the input voltage in V is fed to the integrator in phase, and the feedback voltage ( 1) DAC V i− is integrated in anti-phase at the same time.The output of integrator is described as (1).λ is the gain of integrator in the incremental Σ-Δ ADC, and i represents the number of clock cycles.
( ) ) Data Processing Cyclic ADC has high conversion speed for it needs only M clock cycles for M-bit resolution.In the first cycle, the residue voltage res V (i.e. ( ) is quantized by the 1.5-bit ADC.During the rest cycles, the output voltage ( 1) out V i − is fed to the integrator in phase and the feedback voltage ( 1) The gain of integrator is changed to 1 in the cyclic ADC.
( ) ) The voltage ( ) After 2 N clock cycles, use N 00 , N 01 and N 10 to represent the number of 1 0 ( ) ( ) D i D i which is 00, 01 and 10, respectively.The total sum of N 00 , N 01 and N 10 is 2 N .We can get the residue voltage res V , as shown in (5).
is the M-bit output data of cyclic ADC.
Ignoring the quantization error of the cyclic ADC, we have According to ( 5) and ( 6), we can obtain In our design, the value of λ is 0.5.Equation ( 7) can be simplified as We can see from (8) that the LSB of the two-stage hybrid ADC is and M+N-1 bits resolution can be realized.

A. Implementation
The implementation of this hybrid incremental Σ-Δ/cyclic ADC is shown in Fig. 3.The integrator is of switched-capacitor type and it is symmetrical between the upper part and the lower part.The capacitor H C is used to eliminate the input offset voltage of amplifier.The 1.5-bit ADC is composed of two latch comparators which take up small area and consume little static power.The 1.5bit DAC is made up of multiplexers and logic control circuit.The two stages share the same analog circuit block, which can decrease power and area consumption.This circuit works under the control of signal r φ , 1 φ , 2 φ , 3 φ , m od φ , whose time sequence is shown in Fig. 4. 2 φ is designed to be non-overlap with 1 φ and 3 φ to avoid burr.There are three work modes as shown in Fig. 4. The first is reset mode, in which the amplifier and the integrating capacitors are initialized, and this mode lasts two clock cycles.Incremental Σ-Δ mode and cyclic mode take 256 and 7 clock cycles respectively.So the first stage can provide 8-bit digital data, and the second stage can provide 7 bits.The whole hybrid ADC can realize 14-bit resolution.

B. Pseudo-Differential OTA
The OTA in this hybrid ADC is required to have small power consumption and high gain.To achieve this goal, we adopt the pseudo-differential triple telescope cascode OTA structure as shown in Fig. 5.There is no tail current source in the pseudo-differential OTA, and the positive and negative signal path is independent.Pseudo-differential OTA itself needs no common mode feedback (CMFB) circuit in principle since the common-mode input and output voltage is well-determined during the reset phase.Triple cascode structure is necessary to meet the high open-loop gain requirement.Compared to fully-differential OTA, Pseudo-differential OTA has wider output swing range [10].Compared to folded cascode or two-stage amplifier, telescope cascode OTA has lower power consumption and splendid phase margin.This pseudo-differential OTA can fulfill the requirements of this hybrid ADC.

C. CMFB Module
For high accuracy switched-capacitor circuit, the influence of charge injection cannot be ignored.Although charge injection can be suppressed by optimizing the aspect ratio of switch transistors and dummy transistors partly, there is still some charge ( Q Δ ), which can't be eliminated in each clock cycle.It will cause serious drift of integrator's common-mode output voltage with the accumulation of injection charge in 263 clock cycles.
Though pseudo-differential OTA itself needs no CMFB circuit, we add CMFB module to the integrator to suppress the influence of charge injection [11], as shown in Fig. 3.The capacitor M C is discharged to common-mood ground C M V at 1 φ and forms a common-mode voltage detector at 2 φ .The difference between the common-mode voltage and C M V is fed to the integrator, realizing a CMFB loop whose gain is defined as the ratio of During the incremental sigma-delta mode, the injection charge Q Δ causes integrator's output voltage shift v Δ in every clock cycle, and v Δ is equal to . We have ( 9) and (10) shown as follow.
There are 256 clock cycles in sigma-delta mode.The final common-mode error in sigma-delta mode (256) cm V can be simplified as (13).
There are 7 clock cycles in cyclic mode, and the variation y Δ caused by charge injection is 2 / Q C Δ in each clock cycle.We have ( 14) and (15) shown as follow.
The value of M C should be much smaller than 2 C for the limitation of system bandwidth, so (18) can be simplified as (19).
Take a derivative with respect to (19), we learn

IV. EXPERIMENTAL RESULTS
A test chip of the hybrid ADC is fabricated in 0.35μm 2P4M CMOS technology.The digital circuit used to generate control signals can be shared by all channels.The area of the analog circuit is 0.094 mm 2 .As power supply of the front-end circuit in ROIC is 5V, the analog circuit in this ADC is supplied with 5V and the digital part is supplied with 3.3V.The single-ended input voltage range is 1.2V~3.8V.The ADC works at a clock frequency of 2.5MHz.
The static and dynamic performance is measured by Ultra Flex1600 with 16-bit DAC for input voltage generation.A quasi-DC voltage ramp is used as input for static measurement.The plot of DNL is shown in Fig. 8 with the root mean square (RMS) value of 0.254 LSB.The plot of INL is shown in Fig. 9 with the maximum value of -0.776/+1.56LSB.An 800Hz sinusoidal signal is used as the input signal to perform the dynamic test.The amplitude of sinusoidal signal is 1.3V~3.7V,which is close to the full scale.Fig. 10 shows the power spectral density of the output data.The spectrum shows the pseudo-differential structure with CMFB module suppresses the even harmonic effectively.The measured ENOB achieves 13.43-bit, which is close to the theoretical resolution of 14bit.The test results of the chip are listed in Table I.V. CONCLUSION A 14-bit incremental Σ-Δ/cyclic hybrid ADC based on pseudo-differential OTA is designed and fabricated in 0.35μm CMOS process.This hybrid ADC is a good trade-off of speed and accuracy, and achieves ENOB of 13.43-bit.It is suitable for being integrated in channel of the ROIC for X-ray linear array sensor.

Fig. 2 .
Fig. 2. Architecture of two-stage hybrid ADC After 2 N clock cycles, the Σ-Δ ADC exports the bit stream ( 2 N bits) which can be transferred to N-bit digital data.The output voltage of integrator

−−
is the output voltage of integrator at n-th clock cycle, ( ) cm V n is the common-mode error of output voltage at n-th clock cycle, and ( ) is the output voltage of 1.5-bit DAC at n-th clock cycle.

Fig. 10 .
Fig. 10.Power spectral density of output data Implementation of the hybrid incremental Σ-Δ/cyclic ADC